Clock driven or strobed comparators are well known in the art, and one improved version thereof is shown and described in U.S. patent application Ser. No. 657,414 filed Feb. 12, 1976 now abandoned. In such single-stage comparators, the circuit must perform both the functions of being an amplifer and being a latch. To achieve the desired results, the strobe signal is a symmetrical square-wave clock signal having a 0.5 duty cycle so that the comparator alternates between both functions, each being active 50 percent of the time. The results of the comparison decision are valid and available at the comparator outputs only during the latch portion of the clock period. At increased clock rates where the clock period becomes very small, the output data valid period becomes even smaller, to point where it is unusable in permitting transmission of the data to other circuits.